The technology disclosed herein relates to semiconductor memory devices including a plurality of memory cells, and more particularly, to the control of write operation of memory cells.
FIG. 17 shows a configuration of a memory cell in a typical static random access memory (SRAM). The memory cell includes load transistors QP91 and QP92, drive transistors QN91 and QN92, and access transistors QN93 and QN94. In the memory cell, the potentials of a pair of bit lines BL and /BL are previously precharged high. Data is written to the memory cell as follows. A word line WL is activated (the potential of the word line WL is caused to transition from low to high), and the potential of one of the pair of bit lines BL and /BL is caused to transition from high to low, depending on write data. As a result, the potentials of memory nodes D and ND are changed so that they are complementary, whereby the data is written to the memory cell.
In recent years, as microfabrication technology has advanced, the areas of semiconductor integrated circuits have rapidly decreased. In SRAMs, the size of each transistor included in a memory cell has been largely reduced, leading to an increase in random variations in transistor characteristics. Therefore, it is becoming difficult to ensure a margin for write operation. In general, in order to facilitate write operation (e.g., speed up write operation), it is advantageous in terms of circuit design to reduce the current capability ratio (QP91/QN93) of the load transistor QP91 to the current capability of the access transistor QN93 and the current capability ratio (QP92/QN94) of the load transistor QP92 to the current capability of the access transistor QN94. However, as these current capability ratios decrease, data holding capability (static-noise margin) decreases. If the static-noise margin is not sufficiently ensured, then when a word line is activated, the potentials of the memory nodes D and ND are likely to be reversed (i.e., data is destroyed) in a memory cell which is connected to the activated word line and to which data is not to be written. It is also becoming difficult to ensure the data holding capability due to the increase in random variations in transistor characteristics. In particular, as the threshold voltages of the access transistors QN93 and QN94 decrease due to the random variations, the current capabilities of the access transistors QN93 and QN94 increase (i.e., the current capability ratios (QP91/QN93) and (QP92/QN94) decrease), resulting in a significant degradation in the data holding capability.
As described above, the advances in microfabrication technology have made it more and more difficult to ensure both the write operation margin and the data holding capability in SRAMs. To solve such a problem, Japanese Patent Publication No. S55-64686, (Patent Document 1), Japanese Patent Publication No. 2007-012214 (Patent Document 2), etc. describe a technique of achieving more stable write operation by controlling a power supply voltage VDDM to a memory cell. In this technique, when data is written to a memory cell, the power supply voltage VDDM to the memory cell to which the data is to be written is decreased. As a result, the current capability ratios (QP91/QN93) and (QP92/QN94) decrease, resulting in an improvement in the write operation margin.